This application is related to Korean Application No. 98-33796, filed Aug. 20, 1998, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to integrated circuit devices, and more particularly to integrated circuit devices having signal buffers therein.
Signal buffers have been used frequently as input buffers on integrated circuit chips so that the excessive voltage levels of some external signals can be level-shifted downward to levels that are appropriate for those circuits that reside on the chip. For example, control signals buffers on CMOS-based chips may be used to level-shift external signals at higher TTL levels to lower CMOS levels. This level-shifting operation is typically performed on control signals such as an external clock signal ECLK that is being converted to an internal clock signal PCLK. However, because the level-shifting operation may result in some degree of delay to the internal clock signals and because internal circuits on a chip may need to operate in-sync with the internal clock signal, it may become necessary to delay external data signals on-chip so that sufficient set-up and hold time margins are maintained when processing data in-sync with the internal clock signal. As will be understood by those skilled in the art, such delays may be provided by data buffers having RC delay circuits therein. Unfortunately, RC delay circuits tend to reduce the slope of data signal transitions, consume relatively significant amounts of power and have relatively large unit cell size (i.e., occupy relatively large amounts of chip area). Thus, notwithstanding such attempts to use RC delay circuits to facilitate synchronization between data and internal clock signals, there continues to be a need for devices and methods that provide improved data synchronization capability.
It is therefore an object of the present invention to provide data buffers that can provide sufficient time margins to enable efficient and accurate transfer of synchronous data and methods of buffering data to provide sufficient time margins.
These and other objects, advantages and features of the present invention are provided by a preferred multi-stage data buffer. The data buffer comprises first and second storage devices that are electrically coupled in series and configured so that data can be loaded into the first storage device in-sync with a first clock signal (e.g., external clock signal) and then passed and loaded into the second storage device in-sync with a second clock signal (e.g., internal clock signal). According to a preferred aspect of the present invention, the second clock signal is derived from the first clock signal and may be a delayed version of the first clock signal having an equivalent duty cycle. The buffer also comprises an integrated circuit that operates synchronously with the second clock signal and a transfer device that passes an output of the second storage device to the integrated circuit in-sync with the second clock signal. In this manner, data can be loaded into the integrated circuit in-sync with the same clock signal used to control the integrated circuit even though the data is originally transferred in-sync with another clock signal. A level-shifting inverter may also be provided having an output electrically coupled to an input of the first storage device.
In a most preferred embodiment of the present invention, the data is loaded into the second storage device in-sync with a first edge of the second clock signal and the transfer device passes the output of the second storage device to the integrated circuit in-sync with a second edge of the second clock signal. Here, the first and second edges of the second clock signal may be falling and rising edges, respectively. Moreover, the first storage device comprises a first transmission gate (e.g., CMOS transmission gate) and a first latch having an input electrically coupled to an output of the first transmission gate. Similarly, the second storage device may comprise a second transmission gate having an input electrically coupled to an output of the first latch and a second latch having an input electrically coupled to an output of the second transmission gate.
A preferred method of buffering data is also provided. This preferred method includes the steps of loading a data signal into a first storage device in-sync with a first clock signal and then passing the data signal from the first storage device into a second device, in-sync with a first edge of a second clock signal that is derived from the first clock signal. A step is then performed to pass the data signal from the second storage device to an integrated circuit, in-sync with a second edge of the second clock signal. Based on these aspects of the present invention, data buffers can be provided that secure a sufficient time margin (e.g., set-up time, hold time) to enable efficient and accurate transfer of synchronous data.